| 摘要 |
A semiconductor device for reducing the chip-area on an integrated circuit required for multiple, cascaded MOS transistors, a method of designing said devices and an exemplary portions of circuits using said devices have been achieved. Said novel semiconductor device comprises multiple MOS transistors sharing one common well, one common bulk and are sharing between adjacent MOS transistors each a doped area used as a drain of one transistor and as a source for the other transistor. The chip-area required for the transistors itself of the invented semiconductor device is significantly smaller than the chip-area of conventional transistors having a single well for each transistor. Said MOS transistors, sharing one common well, could be either PMOS transistors or NMOS transistors. The breakdown voltages of said semiconductor device is significantly higher compared to conventional MOS transistors.
|
