| 摘要 |
A data latch circuit of a semiconductor memory device is provided to reduce the total operation current by suppressing a leakage current for latching data in an initial operation period. A data latch circuit of a semiconductor memory device includes an enable controller(100), a data latch(200), and a data output unit(300). The enable controller outputs an enable signal, which is generated correspondingly to the clocking of a data strobe signal, in response to the activation of a power up signal. The data latch is activated in response to the enable signal and latches a data signal. The data output unit is activated in response to the activation of the power up signal and outputs the data, which is latched in the data latch.
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