| 摘要 |
PROBLEM TO BE SOLVED: To provide a timing analysis circuit reducing burden of confirming timing restriction of an actual device. SOLUTION: A bus master 111 synchronizes and transmits a reference clock signal and a synchronization signal showing a prescribed pattern. A re-timing part 112 delays and transmits the synchronization signal transmitted from the bus master 111. A bus slave 121 fetches the synchronization signal transmitted from the re-timing part 112 in synchronization with the reference clock signal, and stores the fetched synchronization signal into a storage part 122. An analysis part 113 adjusts a delay amount of the re-timing part 112, and adjusts the synchronization signal stored in the storage part 122. The analysis part 113 obtains a time lag amount generated between a pattern shown by the synchronization signal stored in the storage part 122 and the prescribed pattern. COPYRIGHT: (C)2008,JPO&INPIT
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