Semiconductor memory device for performing refresh operation and semiconductor memory system including the same

摘要

A semiconductor memory device includes: a memory cell array including a plurality of word lines; a word line driving unit suitable for activating a first word line among the plurality of word lines corresponding to an input address signal; an activation time detection unit suitable for enabling a detection signal by detecting an activation time of the first word line; an address latch unit suitable for latching an address information for a second word line corresponding to the first word line in response to the detection signal; and an address output unit suitable for providing the word line driving unit with the latched address information for the second word line during a refresh operation.

主权项

1. A semiconductor memory device, comprising:
a memory cell array including a plurality of word lines; a word line driving unit suitable for activating a first word line among the plurality of word lines corresponding to an input address signal; an activation time detection unit suitable for enabling a detection signal by detecting an activation time of the first word line; an address latch unit suitable for latching an address information for a second word line corresponding to the first word line in response to the detection signal; and an address output unit suitable for providing the word line driving unit with the latched address information for the second word line during a refresh operation, wherein the activation time detection unit includes:
a reference value generator suitable for generating a reference value; andan activation time comparator suitable for enabling the detection signal by comparing the activation time of the first word line with the reference value, and wherein the reference value depends on an operation state of the memory cell array.