| 摘要 |
The cryptographic bus architecture prevents usage of side channel information by Differential Power Attacks (DPA) by randomly toggling the polarity of a target bit at a data bus driver. The bus architecture comprises bi-directional drivers 315, 317 connected by a bus 316. An N-bit random number generator 313 has N outputs 314, wherein each output comprises one bit. The value of each random bit is used to toggle a driver. i.e. change its polarity, and drive the internal bus so as to defeat correlation. The chance of having a "0" or "1" will be approximately 0.5 due to the randomization of the polarity. Preferably the polarity control line is probe-resistant. Other embodiments are disclosed for preventing information leakage attacks that utilise timeline alignment, including inserting a random number of instructions into an encryption algorithm such that the leaked information cannot be aligned in time to allow attacker to break the encryption. |
