| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a cache memory for performing cache hit determination of an input address in parallel with cache hit determination of a prefetch address which is not limited to the adjacent address of the input address. Ž<P>SOLUTION: An address generation part 16 generates a prefetch index address included in a prefetch address based on an input address supplied from a higher-level device. Each way included in a tag memory 11 has a memory part which receives an input index address in the input address in parallel with the prefetch index address and output a first tag address obtained in access by the input index address in parallel with a second tag address obtained in access by the prefetch index address. Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž
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