OUTPUT CONTROL CIRCUIT FOR SEMICONDUCTOR APPARATUS AND OUTPUT DRIVING CIRCUIT INCLUDING THE SAME

摘要

An output control circuit may include a period setting signal generation unit configured to output a setup signal enabled during a designated period, in response to a delayed locked loop (DLL) locking signal and an output enable reset signal. The output control circuit may also include a clock division unit configured to divide an internal clock at a preset division ratio in response to the setup signal, and output a divided clock. In addition, the output control circuit may include a shift unit configured to shift the setup signal by a preset first time in response to the divided clock, and output a first delayed setup signal. Further, the output control circuit may include an output unit configured to receive and process the first delayed setup signal in response to the divided clock, and output the output enable reset signal.

主权项

1. An output driving circuit comprising:
an output enable reset signal generation circuit configured to generate a first delayed setup signal by shifting a setup signal in synchronization with a divided clock obtained by dividing an internal clock in response to a delayed locked loop (DLL) locking signal, and generate an output enable reset signal by processing the first delayed setup signal in response to the divided clock; a delay circuit configured to delay the output enable reset signal by a preset time; a counting unit configured to output a counting signal corresponding to a period defined by the output enable reset signal and an output signal of the delay circuit, in response to the internal clock; and an output enable signal output unit configured to output an output enable signal in response to the counting signal and CAS latency information.