发明名称 |
RSA ALGORITHM ACCELERATION PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS |
摘要 |
A processor includes a decode unit to decode an instruction. The instruction indicates a first 64-bit source operand having a first 64-bit value, indicates a second 64-bit source operand having a second 64-bit value, indicates a third 64-bit source operand having a third 64-bit value, and indicates a fourth 64-bit source operand having a fourth 64-bit value. An execution unit is coupled with the decode unit. The execution unit is operable, in response to the instruction, to store a result. The result includes the first 64-bit value multiplied by the second 64-bit value added to the third 64-bit value added to the fourth 64-bit value. The execution unit may store a 64-bit least significant half of the result in a first 64-bit destination operand indicated by the instruction, and store a 64-bit most significant half of the result in a second 64-bit destination operand indicated by the instruction. |
申请公布号 |
US2016308676(A1) |
申请公布日期 |
2016.10.20 |
申请号 |
US201315102637 |
申请日期 |
2013.12.28 |
申请人 |
LU Yang;SUN Xiangzheng;QIAO Nan Stan;INTEL CORPORATION |
发明人 |
Lu Yang;Sun Xiangzheng;Qiao Nan |
分类号 |
H04L9/30;G06F9/30;G06F7/72 |
主分类号 |
H04L9/30 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
Shanghai CN |