SOLID-STATE IMAGE PICKUP DEVICE, AND IMAGE PICKUP DEVICE

摘要

A solid-state image pickup device includes: a pixel portion in which a plurality of pixels are arrayed in matrix; and an Analog-Digital converter. The Analog-Digital converter converts pixel signals, which are generated in the pixel portion, from analog signals into digital signals. The Analog-Digital converter includes: a comparator; and a counter. The comparator compares the analog signals, each of which corresponds to each of the plurality of pixels, with a reference signal. The comparator includes: a first differential transistor to which the reference signal is input; a second differential transistor to which the analog signals are input; a first load transistor; a second load transistor; and a current source transistor. A fluctuation of a voltage between a gate and a source of the first differential transistor is suppressed. This fluctuation follows a voltage fluctuation of a node connected commonly to the second differential transistor and the second load transistor.

主权项

1. A solid-state image pickup device comprising:
a pixel portion in which a plurality of pixels performing photoelectric conversion are arrayed in matrix; and an Analog-Digital converter that converts pixel signals, which are generated in the pixel portion, from analog signals into digital signals, wherein the Analog-Digital converter includes: a comparator which is disposed for each of pixel columns and compares the analog signals, each of which corresponds to each of the plurality of pixels, with a reference signal; and a counter which is disposed so as to correspond to the comparator and obtains the digital signals by counting periods during which the comparator compares the analog signals with the reference signal, the comparator includes: a first differential transistor to which the reference signal is input; a second differential transistor to which the analog signals are input; a first load transistor connected between a drain terminal of the first differential transistor and a power supply; a second load transistor connected between a drain terminal of the second differential transistor and the power supply; and a current source transistor connected between a ground and source terminals of the first differential transistor and the second differential transistor, wherein a fluctuation of a voltage between a gate and a source of the first differential transistor is suppressed, the fluctuation following a voltage fluctuation of a node connected commonly to the second differential transistor and the second load transistor.