MULTI-CHIP PACKAGE STRUCTURE, WAFER LEVEL CHIP PACKAGE STRUCTURE AND MANUFACTURING PROCESS THEREOF

摘要

A multi-chip package structure includes a first chip, at least one blocking structure, a plurality of first conductive bumps, a second chip, a plurality of second conductive bumps and an underfill. The first chip has a chip connecting zone, a plurality of first inner pads in the chip connecting zone and a plurality of first outer pads outside of the chip connecting zone. The blocking structure is disposed between the first inner pads and the first outer pads and surrounds the first inner pads. The first conductive bumps are disposed on the first outer pads. The second chip is flipped on the chip connecting zone and has a plurality of second pads. The second conductive bumps are disposed between the first inner pads and the second pads. The underfill is disposed between the first chip and the second chip so as to cover the second conductive bumps.

主权项

1. A multi-chip package structure, comprising:
a first chip, having a chip connecting zone, a plurality of first inner pads located in the chip connecting zone and a plurality of first outer pads located outside of the chip connecting zone; at least one blocking structure, disposed on a region outside of the chip connecting zone of the first chip and between the first inner pads and the first outer pads to surround the first inner pads; a plurality of first conductive bumps, disposed on the first outer pads; a second chip, flipped on the chip connecting zone, and the second chip having a plurality of second pads; a plurality of second conductive bumps, located between the first inner pads and the second pads, and each of the first inner pads being electrically connected with the corresponding second pad through the corresponding second conductive bump; and an underfill, located between the first chip and the second chip so as to cover the second conductive bumps.