Decoding method, memory storage device and memory controlling circuit unit

摘要

A decoding method for a parity check code, a memory storage device and a memory controlling circuit unit are provided. The decoding method includes: reading a codeword belonging to the parity check code from a rewritable non-volatile memory module, wherein the codeword includes message bits and first parity bits; performing an encoding procedure of the parity check code on the message bits to generate second parity bits; and generating a plurality of syndromes corresponding to the codeword according to the first parity bits and the second parity bits, wherein the syndromes are used to determine whether the codeword is a valid codeword. Accordingly, a complexity of a decoding circuit is decreased.

主权项

1. A decoding method for a parity check code, comprising:
reading a codeword belonging to the parity check code from a rewritable non-volatile memory module, wherein the codeword comprises a plurality of first message bits and a plurality of first parity bits, and the parity check code corresponds to a parity check matrix and a generation matrix; performing an encoding procedure of the parity check code on the first message bits to generate a plurality of second parity bits; and generating a plurality of syndromes corresponding to the codeword according to the first parity bits and the second parity bits, wherein the syndromes are used to determine whether the codeword is a valid codeword, wherein the parity check matrix comprises a message part matrix and a parity part matrix, and the step of generating the syndromes corresponding to the codeword according to the first parity bits and the second parity bits comprises: adding a vector (P1) generated by the first parity bits to a vector (P2) generated by the second parity bits to generate a first vector; and multiplying the parity part matrix by the first vector to generate the syndromes (S) corresponding to the codeword, wherein the step of performing the encoding procedure of the parity check code on the first message bits to generate the second parity bits comprises: multiplying a vector (M1) generated by the first message bits by the generation matrix to generate the second parity bits, so that a result generated by multiplying the parity check matrix by a vector (M1 P2) constituted by the first message bits and the second parity bits is a zero vector.