| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit capable of suppressing the increase of data transfer time between a plurality of circuit blocks different in power supply voltage and clock frequency. SOLUTION: A data transfer circuit 1 comprises: a first transfer circuit 11 for inputting a first transfer signal d00 from a first circuit block B1; a second transfer circuit 12 for inputting a second transfer signal d01 from the first circuit block B1; a third transfer circuit 21 for inputting a first transfer signal d10 and an inverse signal d10n of the first transfer signal d10 outputted from the first transfer circuit 11, respectively, and outputting a first transfer signal d20 in accordance with a response signal a2 from a second circuit block B2; and a fourth transfer circuit 22 for inputting a second transfer signal d11 and an inverse signal d11n of the second transfer signal d11 outputted from the second transfer circuit 12, respectively, and outputting a second transfer signal d21 in accordance with the response signal a2. COPYRIGHT: (C)2007,JPO&INPIT
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