System and method of circuit layout for multiple cells

摘要

A circuit layout method comprises inputting layout data into a circuit layout system. The layout data represents a plurality of patterns in a plurality of cells. Each pattern of the plurality of patterns has a plurality of runs, ends, and corners. The method also comprises specifying a plurality of G1-rule criteria. The method further comprises reviewing a representation of G0-space and G0 rule violations for each cell of the plurality of cells. The method additionally comprises inputting an adjustment to the layout data. The method also comprises reviewing a representation of adjusted cell edge spacings, and selecting to output a final layout.

主权项

1. A circuit layout method comprising:
inputting layout data into a circuit layout system, said layout data representing a plurality of patterns in a plurality of cells, each pattern of the plurality of patterns having a plurality of runs, ends, and corners; identifying a next edge pattern within a cell of the plurality of cells, wherein the next edge pattern is not a pattern closest to an edge of the cell of the plurality of cells; inputting an adjustment to the layout data based on at least one of
whether a spacing between the next edge pattern and the edge of the cell of the plurality of cells is less than a first predetermined distance, orwhether a spacing between the next edge pattern and a closest pattern within another cell of the plurality of cells is less than a second predetermined distance; outputting a representation of adjusted cell edge spacings; and outputting a final layout based at least in part on the adjustment for implementation in a semiconductor fabrication process.