发明名称 SEMICONDUCTOR DEVICES OF COMPOUND SEMICONDUCTOR MATERIAL
摘要 1347874 Etching AGENCY OF INDUSTRIAL SCIENCE & TECHNOLOGY 27 April 1971 [28 April 1970 14 Sept 1970] 11711/71 Heading B6J [Also in Division H1] A device comprising a monocrystalline compound semi-conductor substrate is provided with an inwardly splayed-out groove wider at its base than at the substrate surface by selective use of suitable etchants on particular crystal planes and along particular crystal axes. In an example, etching GaAs with a Br 2 -CH 3 OH etchant on to a (100) plane through a mask defining an aperture aligned along the [011] direction will result in a groove of the desired cross-section. The use of (211) or (311) planes results in inwardly splayed-out grooves of asymmetrical cross-section. Other semi-conductors to which the invention may be applied include GaP, GaAs x P 1-x , ZnS and CdS, masking being effected by means of a layer of Al 2 O 3 or SiO 2 deposited by electron beam evaporation. Fig. 6 shows a monolithic assembly of Gunn diodes, each of which is situated in a bridge 8 defined by etching a pair of inwardly splayedout grooves so close together that they merge at a level spaced from the surface. The space between the bridges 8 may provide air-cooling or may be filled with a heat conducting material. Fig. 8 shows a Schottky-barrier-gate field effect transistor wherein the evaporated Schottkybarrier-gate metal 14 is situated on an N-type epitaxial layer 13 within an inwardly splayedout groove 18 etched through an N<SP>+</SP> epitaxial or diffused layer 17. The lateral edges of the gate 14 are spaced from the edges of the groove 18 due to the masking effect of the overhanging upper edges of the groove 18. Ohmic source and drain electrodes may be of the same metal as the Schottky-barrier-gate 14 or may, for GaAs, be of Sn, Pt, Au-In-Ge or Sn-Ag. In the latter alternative an upper layer of the Schottkybarrier metal may also be provided. Several integrated circuits including one or more Schottky-barrier-gate FET's are described. A PN junction gate FET may also be formed by ion bombardment of a suitable dopant into a part of the base of an inwardly splayed-out groove, masking being effected by the combination of the overhanging upper edges of the groove and a metal layer on the upper surface of the substrate.
申请公布号 GB1347874(A) 申请公布日期 1974.02.27
申请号 GB19710011711 申请日期 1971.04.27
申请人 AGENCY OF INDUSTRIAL SCIENCE TECHNOLOGY 发明人
分类号 H01L21/306;H01L27/00;H01L29/00;H01L29/04;(IPC1-7):H01L5/00 主分类号 H01L21/306
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