| 摘要 |
A threshold circuit for reducing the time required to discharge an input voltage at a data node from a first to a second logic level. The circuit includes a controllable shunt field effect transistor connected to provide a secondary discharge path between the data node and a voltage reference of the second logic level. As the input voltage begins to discharge along a primary discharge path, the resulting change in the input voltage level is fed back to the control electrode of the shunt transistor to turn on the shunt transistor and connect the data node to the voltage reference along the secondary discharge path to more quickly discharge the input voltage to the second logic level. In the preferred embodiment, the threshold circuit is connected to the output node of a read-only memory to reduce the read-out time of logic information stored in the memory.
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