Opto-electronic detector parasitic signal discriminator - has internal clock synchronising detector with comparator

摘要

The internal clock (CK) is connected to a detector (De) and a comparator (P1) to synchronise them, the comparator (P1) providing an output signal (F) for zero-resetting a counter (R). The detector is connected to the count input (H) of the counter (R) via a logic gate (P2), which also receives the inverse of the output signal (S) of an output of the counter (R). The output signal of the discriminator is formed by the product of the latter counter output signal (S) and its inverse (S), this having a first logic state when the detector (De) detects an object, and a second logic state for all other possible cases, e.g. when parasitic signals or no signals are detected. Pref. the logic gate is a NOT-AND gate.