| 摘要 |
<p>Binary signal train and clock pulses are applied to the code converter gate (203); and there is a delay line (204), which is connected to the code converter gate whose time delay is approx. half the pulse width; an adder (205) adds the delay line output signals to clock pulses, and a frequency divider (206), connected to the adder, divides the output frequency of the latter, so that the binary signal train is converted into transmission signals in a different code. The signal train is applied to a first terminal (201) which is connected only to the gate (203). The clock pulses are applied to the second terminal (202) which is connected to the gate and is also connected directly to the adder (205).</p> |
