Circuit arrangement for a selective signal receiver, particularly for use in telephone systems

摘要

Selective digital signal receiver wherein the time distances between zero crossings of the input voltage are measured with a counter. The zero-crossing counter is preceded by a circuit which, when a zero crossing occurs, is changed to the "on" state, resulting in a counting pulse for the counter, and remains in this state for a dwell time which is only little shorter than the signal-frequency half cycle. Thus, interference pulses can no longer invalidate the counting result of each signal-recognition operation.