| 摘要 |
A complementary integrated circuit in MOS technology contains at least one P-channel FET (18) with insulated gate (24) and one N-channel FET (16) with insulated gate (26). A closed geometry results in fast transistors with a high packing density. Drain zones (38 and 42) are surrounded by frame-like gate structures (24 and 26) which, in turn, are surrounded by source zones (40 and 44). To insulate the transistors, a layer (22), which is also closed in the manner of a frame, of conductive material is provided which acts as insulating gate. This also results in space-saving isolation of the transistors. In production, a self-aligning gate technique is used, the layer (22) being produced at the same time as the gates (24, 26). A single mask setting can be used for making a plurality of diffusions. <IMAGE> |
