| 摘要 |
Multiplication apparatus is described which operates on 2's complement operands by a series of partial product formation cycles and generates the product of the operands in an accumulator register. For each cycle, a pair of the n multiplier bits is processed, right to left. On the basis of each bit pair configuration and the next multiplier bit, the accumulated partial product is shifted 2 bits right and a selected multiple (0, 1/2 or 1) of the multiplicand is added to or subtracted from the partial product accumulator register. Special initialization logic is restricted to loading the multiplier into an operand register, shifted one bit to the left, with a zero fill in the least significant bit position, and no special logic is required for correct termination after n/2 cycles, regardless of operand sign combinations. |
