| 摘要 |
1507638 APC systems PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd 18 Nov 1976 [21 Nov 1975] 48091/76 Heading H3A In a synchronous data receiver for receiving FSK or vestigial sideband with suppressed carrier modulated binary data signals, an arrangement for synchronizing a local clock 7 with the received data and suitable for symbol regeneration or synchronous demodulation comprises a non-linear circuit 4 e.g. a squarer, a phase lock loop adapted for avoiding large phase fluctuations caused by a long series of identical symbols in the input data and including the clock 7, phase comparators 11, 12 connected to receive the data via 4 and via a circuit 19, signals which are different in frequency but related to the clock and a circuit 20 which combines the detector outputs to form a control signal for the clock. When echo modulation is used and the data components received by the comparators 11, 12 are integral multiples of the basic symbol rate, the circuit 19 may be as in Fig. 3 (not shown). In an embodiment the signal is switched between f c and ¢f c by the data and the squaring circuit 4 produces therefrom 2f c and f c . The oscillator operates at 2f c and is divided by 2 at 21 so that one or other of the phase comparators provides a reference signal when data is unchanging. |
