发明名称 |
Localized fast bulk storage in a multi-node computer system |
摘要 |
A high performance computing (HPC) system includes computing blades having a first region that includes computing circuit boards having processors for performing a computation, and a second region that includes non-volatile memory for use in performing the computation. The regions are connected by a plurality of power connectors that convey power from the computing circuit boards to the memory, and a plurality of data connectors that convey data between the first and second regions. The power and data connectors are configured redundantly so that failure of a computing circuit board, a power connector, or a data connector does not interrupt the computation. A method of performing such a computation, and a computer program product implementing the method, are also disclosed. |
申请公布号 |
US9477592(B2) |
申请公布日期 |
2016.10.25 |
申请号 |
US201313931861 |
申请日期 |
2013.06.29 |
申请人 |
Silicon Graphics International Corp. |
发明人 |
Dean Steven |
分类号 |
G06F12/02;G06F1/26;G06F3/06;G06F11/20 |
主分类号 |
G06F12/02 |
代理机构 |
Sunstein Kann Murphy & Timbers LLP |
代理人 |
Sunstein Kann Murphy & Timbers LLP |
主权项 |
1. An HPC system having a plurality of housings, each housing including one or more computing blades that each have at least one computing circuit boards, wherein a plurality of the computing circuit boards in the HPC system are configured to cooperate to perform a computation defined by a user of the HPC system, and wherein at least one given housing comprises:
a computing region having a plurality of computing circuit boards that are used in performing the computation, each computing circuit board receiving power from a different power source; a data storing region having a non-volatile memory that is used in performing the computation; and a plurality of riser boards, each riser board being mechanically and electrically coupled to a plurality of computing circuit boards in the computing region and physically extending into the data storing region, each riser board comprising a plurality of power connectors that convey power from the coupled computing circuit boards in the computing region to the data storing region, and a plurality of data connectors that convey data for use in performing the computation between the coupled computing circuit boards in the computing region and the non-volatile memory in the data storing region; wherein the riser boards are configured so that the non-volatile memory in the data storing region are usable, by a computing circuit board in a housing other than the given housing, for performing the computation after failure of one or more of: a power source, a computing circuit board in the computing region, a riser board, a power connector, or a data connector. |
地址 |
Milpitas CA US |