发明名称 Recording process write pulse generation - uses master slave coupled flipflops with comparator output stage to convert phase encoded binary information
摘要 <p>The phase encoding of binary information into write pulses for recording processes is provided by clocked flip-flops operating into a comparator stage. A clock generator (5) produces out of phase signals (51, 52) of the same frequency to enter input signal data (E1) into R-S flip-flops (1, 2) operating in a master-slave mode. An equivalence gate (4) generates an output when the states of the flip-flops are the same. The resulting signal is entered into an output flip-flop (3) by a third phase shifted clock signal of twice the base frequency. the output (A3) is used as a write signal.</p>
申请公布号 DE2723054(A1) 申请公布日期 1978.01.05
申请号 DE19772723054 申请日期 1977.05.21
申请人 VEB KOMBINAT ZENTRONIK 发明人 WIRTH,HANS-JUERGEN,DIPL.-ING.
分类号 G11B20/14;(IPC1-7):11B5/09 主分类号 G11B20/14
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