发明名称 Memory access system
摘要 An input/output processing system includes an input/output processing unit and a read only memory (ROM) and a read/write memory. The ROM is coded to include instructions of a number of control routines. The read/write memory includes locations for storing instructions and data. The processing unit includes a plurality of registers for storing information used in developing addresses for accessing each memory. It further includes a control register for storing information for controlling accesses to the memories and a steering register which operatively couples to the control register and stores information designating which one of the memories is to be accessed. The processing unit is conditioned to exclusively OR the information in the control register with the information contained in one of the plurality of registers. By logically combining the contents of the control register and contents of another register during each address development operation, the processing unit is able to switch between the two memories as desired. When it is desired to start or stop accessing instructions from ROM, the processing unit is conditioned to perform an OR or AND operation respectively upon the contents of the control register with the contents of the other register and place the result in the control register.
申请公布号 US4124891(A) 申请公布日期 1978.11.07
申请号 US19760742814 申请日期 1976.11.18
申请人 HONEYWELL INFORMATION SYSTEMS INC. 发明人 WELLER, III, EDWARD F.;PORTER, MARION G.
分类号 G06F3/00;G06F13/00;G06F13/12;G11C7/00;G11C8/00;(IPC1-7):G06F13/00 主分类号 G06F3/00
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