| 摘要 |
The exchange includes an input-output bus having a plurality of lines, predetermined ones of which are coupled to a different one of a plurality of peripheral information units. Each of the units are coupled to an associated one of the predetermined one of the lines through a transmission gate under control of an address detector. A random access memory is coupled to each of the predetermined ones of the plurality of lines to sequentially store and release the information of an addressed unit in the exchange selectively on command. A stored program is coupled to the random access memory to selectively command the random access memory and is coupled to others of the plurality of lines which are in turn coupled to the address detectors to selectively control the routing of the information of an addressed unit through the exchange. A timing source coupled to further ones of the plurality of lines provides an incoming timing signal and an outgoing timing signal cooperating with the stored program to selectively control the passage of the information of an addressed unit through the exchange to an addressed one of the units.
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