发明名称 Valid memory address pin elimination
摘要 A digital data processor on a single monolithic integrated circuit chip is provided which uses one less pin. The elimination of the pin is accomplished by using, internally to the processor, a valid memory address signal to gate information from the address but to an address output line. Whenever an address is not present on the address bus all logic "1's" are generated on the address output bus.
申请公布号 US4330842(A) 申请公布日期 1982.05.18
申请号 US19780939723 申请日期 1978.09.05
申请人 DANIELS, R. GARY;BENNETT, THOMAS H.;WILES, MICHAEL F. 发明人 DANIELS, R. GARY;BENNETT, THOMAS H.;WILES, MICHAEL F.
分类号 G06F1/22;G06F13/42;(IPC1-7):G06F3/00;G06F13/00 主分类号 G06F1/22
代理机构 代理人
主权项
地址