| 摘要 |
PURPOSE:To minimize the occupying area of a gate protective resistor, and to miniaturize a chip by preparing a load resistor of a memory cell section in a MIS type static RAM and the protective resistor of a peripheral circuit section according to the same process by upper layer poly Si. CONSTITUTION:A resistor RIN and a diode D are inserted between a signal imput pad section VIN and a gate section of a CMOS inverter, and used as a protective circuit. The resistor RIN7 is prepared by doping phosphorus (approximately 150OMEGA/unit area) to the poly Si of the second layer, to which ions are not doped and which is manufactured as the load resistor of the cell section, at the same time as a VCC wiring section. One end of the RIN7 is connected to an N<+> region 4 of the diode D formed at the same time as the source and drain regions of an N type FET, and the other end is connected to an input pad 21 through an Al wiring 9. Accordingly, the occupying area can be decreased largely as compared to the case when a poly Si layer for a gate is used as the protective resistor, and a miniaturized circuit can be prepared without employing a special process.
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