| 摘要 |
<p>A microprocessor (10), having a memory element (18) containing a plurality of multi-bit instruction words, an arithmetic logic (ALU) unit (16) coupled to the memory element (18) and responsive to at least a portion of each of the instruction words for performing data manipulations, and a controller (20) for generating address signals that are communicated to the memory element (18) to cause sequential access of the instruction words, includes a storage element (40) that interconnects certain of the signal lines (30.32) that communicate the instruction words to the ALU (16) to the controller (20). In response to a first predetermined instruction word the storage element (40) receives and stores the portion of the instruction word being conducted to the ALU (16). In response to a second predetermined instruction word, the content of the storage element (40) is transferred to the controller (20) to form an address signal.</p> |
