发明名称 SIGNALOVERFORINGSANORDNING
摘要 A time slot interchanger is disclosed for selecting and buffering digital signals between buses. The arrangement is particularly useful in forming conferences in a distributed digital time division system. In one embodiment, a clock is used to generate time signals corresponding to time slots of the first bus. These signals are sequentially provided to an associative memory and when a match occurs between the provided signal and a priorly stored time slot identity, an enable signal is provided. The enable signal has a time identity with a first bus time slot and a physical identity with a particular second bus time slot. The enable signal is used to gate into a second memory the time slot signal associated with the time identity at the storage location in the second memory corresponding with the particular time slot of the second bus associated with the enable signal. The signal samples are then sequentially removed from the second memory.
申请公布号 SE8202233(L) 申请公布日期 1982.10.24
申请号 SE19820002233 申请日期 1982.04.07
申请人 WESTERN ELECTRIC CO 发明人 MOFFITT B S;ROSS A R
分类号 H04M3/56;H04N7/15;H04Q11/04;H04Q11/08;(IPC1-7):H04M3/56 主分类号 H04M3/56
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