发明名称 SYSTEM AND METHOD FOR EVENT MONITORING IN CACHE COHERENCE PROTOCOLS WITHOUT EXPLICIT INVALIDATIONS
摘要 Synchronization events associated with cache coherence are monitored without using invalidations. A callback-read is issued to a memory address associated with the synchronization event, which callback-read either reads the last value written in the memory address or blocks until a next write takes place in the memory address and reads a newly written value.
申请公布号 US2016321181(A1) 申请公布日期 2016.11.03
申请号 US201515108948 申请日期 2015.01.02
申请人 KAXIRAS Stefanos;ROS Alberto 发明人 KAXIRAS Stefanos;ROS Alberto
分类号 G06F12/0831;G06F13/16;G06F12/128;G06F12/084 主分类号 G06F12/0831
代理机构 代理人
主权项 1. A computer system comprising: multiple processor cores; at least one local cache memory associated with and operatively coupled to each core for storing one or more cache lines accessible only by the associated core; a shared memory, the shared memory being operatively coupled to the local cache memories and accessible by the cores, the shared memory being capable of storing a plurality of cache lines; and wherein a core issuing a callback-read to a memory address either reads the last value written in this address or blocks until the next write takes place in the memory address and then reads a new value such that the callback-read enables event monitoring for coherence of the at least one local cache and the shared memory without using explicit invalidations.
地址 Uppsala SE