发明名称 INFORMATION PROCESSING APPARATUS AND COMPILING METHOD
摘要 A memory stores code including a plurality of functions and a plurality of function calls each calling one of the plurality of functions. A processor calculates, for each of the plurality of functions, a plurality of index values including a first index value indicating an iteration status of a loop in the function and a second index value indicating the code size of the function. The processor calculates, for each of the plurality of function calls, an evaluation value based on the plurality of index values that are calculated for the function called by the function call. The processor selects one or more of the plurality of function calls, based on the evaluation value, and inlines the selected function calls.
申请公布号 US2016321048(A1) 申请公布日期 2016.11.03
申请号 US201615070048 申请日期 2016.03.15
申请人 FUJITSU LIMITED 发明人 Matsuura Takayuki
分类号 G06F9/45 主分类号 G06F9/45
代理机构 代理人
主权项 1. An information processing apparatus comprising: a memory configured to store code including a plurality of functions and a plurality of function calls, each of the plurality of function calls calling one of the plurality of functions; and a processor configured to perform a procedure including: calculating, for each of the plurality of functions included in the code, a plurality of index values including a first index value and a second index value, the first index value indicating an iteration status of a loop in the function, the second index value indicating a code size of the function; calculating, for each of the plurality of function calls included in the code, an evaluation value based on the plurality of index values that are calculated for the function called by the function call; and selecting one or more of the plurality of function calls, based on the evaluation value, and inlining the selected one or more function calls.
地址 Kawasaki-shi JP