| 摘要 |
PURPOSE:To realize a very high-speed and large-capacity memory device, by accessing an extension memory by address data generated by adding contents of a base address pointer and input address data. CONSTITUTION:A basic memory 9 and an extension memory 10 are connected to a data bus 3 connected to a CPU1, and write data from the CPU1 and read data from these memories 9 and 10 are transferred through the bus 3. A memory controlling part 11 is connected to an address bus 2 and the bus 3, and, for example, 16-bit address data inputted from the CPU1 is extended to generate 20-bit address data and is inputted to memories 9 and 10 through a memory address bus 12. Consequently, the bus 2 connected to the CPU1 is used to transfer address data from the CPU1 to the controlling part 11, each input/ output interface 5, etc. |
