| 摘要 |
PCT No. PCT/US80/01149 Sec. 371 Date Sep. 8, 1980 Sec. 102(e) Date Sep. 8, 1980 PCT Filed Sep. 8, 1980 PCT Pub. No. WO82/00917 PCT Pub. Date Mar. 18, 1982.A circuit for burning-in an integrated circuit memory receives a two state signal at a burn-in terminal (168). A clock refresh signal is provided to a refresh terminal (170) which drives a refresh counter (192). A sequence of addresses are generated by the refresh counter (192) and provided to row decoders (194) and column decoders (196). When the burn-in command provided to the burn-in terminal (168) is at a first state, sense amplifiers (132) within a memory array (107) are disabled so that pullup circuits (148) elevate digit lines (116, 118) to a high voltage level. The high voltage level is transferred into memory cell storage capacitors (120, 122). When the burn-in command is in either the first or the second state, the refresh signal causes a row clock chain generator (176) to generate row clock signals and a column clock chain generator (178) to generate column clock signals. The addresses generated by the refresh counter together with the signals produced by the row and column clock generators cause the memory cells (120), sense amplifier (132) and associated circuitry within the memory array (107) to be burned-in. The memory array (107) can be exercised with signals received through only 4 terminals to make possible concurrent exercising of a plurality of integrated circuits on a tape having no crossovers of conductor lines.
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