Processor storage management system.

摘要

The invention relates to a system for managing the physical store of a processor. This system comprises a table (T) of segment-descriptor registers, means for converting a virtual address into a physical address, the virtual address containing at least one virtual page number (VP), the binary value of a tracking index (VI) for the first descriptor register and the value of the offset (PO) of the start of the physical segment, relative to the start of the corresponding real page. This system is characterised in that it further comprises a base register (BA) loaded with the base address of the first descriptor register, the table (T) of descriptor registers having inputs which are connected to the outputs of a logic adder (OU1) which receives the binary value of the base address of the first descriptor register and the binary value of the index (VI) corresponding to this register, the outputs of the adder tracking one of the inputs of the table (T). Application to the management of memories by pagination and segmentation. <IMAGE>