| 摘要 |
PURPOSE:To control the resistance value of the load element of a memory cell simply when the titled semiconductor device is used as the load element while improving the degree of integration of the element by sufficiently increasing the value of the inverse currents of a P-N junction element. CONSTITUTION:P<-> type silicon is deposited onto the surface of an insulating substrate such as a sapphire substrate 31, and a silicon layer 32 is formed. When the silicon layer 32 and the silicon layers 321, 322 of sections previously etched are oxidized and an SiO2 film 33 and an Si3N4 film 34 are removed through the etching treatment of the surface of the silicon layer 32 after completion of oxidation, the P<-> type silicon layer 32 is isolated from other regions by SiO2 layers 361, 362, and changed into an island region. When oxidizing, a section up to the depth of approximately 4,000Angstrom from the surface of the silicon layer 32 exposed from a through hole 35 is oxidized and converted into an SiO2 layer 363, and the silicon layer positioned at the lower section of the SiO2 layer 363 is turned into a P type layer 37. A diode 20 or 21 is obtained as the P-N junction element using an N<+> type layer 42 as a cathode region and the P type layer 37 as an anode region. |
