| 摘要 |
PURPOSE:To speed up bit inverting and rearranging processing by using an address generating circuit as a generating circuit for a bit-inverted address for a data processor. CONSTITUTION:When the rearrangement of array data is started after initializing operation, a clock signal 13 is sent to a bit invertion generating circuit 1 and a memory control circuit 8 because a gate 11 is opened. The bit inversion generating circuit 1 multiplies the subscript value k' of an array a' (k') by data length L to output the product to a memory control circuit 8. The control circuit 8 reads one element a (k) of an array from an external part 10 and writes a'(k') in a memory 9. The subscript k' is compared with the value of a stop pattern when they coincide with each other, the gate 1 is closed to add the value of the subscript k' to the value of an addition pattern, setting the result as the value of the subscript k'. This operation is carried out every time a clock signal 13 is supplied to write the array a(k) from the external part 10 in a memory 9 successively and it is sent out as the array a'(k) to the outside 10. |
