| 摘要 |
<p>A memory addressing system includes an addressable memory (70) provided with error checking and correction (ECC) circuits (50A, 50B) which include output latches (54B, 54D) adapted to latch corrected data read from the memory (70). An applied memory address is compared in a comparator (30) with a previous memory address stored in an address latch (20) and if a match is detected, a match signal is effective to inhibit the occurrence of the next memory cycle and to activate a decoder (40) coupled to the output of the ECC circuits (50A, 50B) to cause transfer to the system bus (43) of selected data from the ECC latches (54B, 54D). If no match is detected, a memory cycle is initiated to access the desired data in the memory (70). A high-speed memory operation is thus achieved utilizing simple circuitry.</p> |
