| 摘要 |
PURPOSE:To reduce the required number of delay circuits, by compensating the delay time of a delay circuit by a frequency divider, in a circuit inserting a narrow pulse of opposite polarity for each prescribed length when the same binary codes are consecutive for a prescribed length or over. CONSTITUTION:A binary signal (a) representing consecutively the same code is delayed by a pulse width T1 at a delay circuit 2. The signal (a) and the delayed signal (b) pass through an exclusive OR circuit 3a, an inverted output (c) of the circuit 3a is inputted to an inverting output f1 of the frequency division circuit comprising an FF circuit 15 and to an AND circuit 15, the output d1 passes through a delay circuit 13 having (T2-T3)/2 of delay time, one of the output e1 is applied to an AND circuit as it is and the other is applied to the AND circuit after being inverted at a delay circuit 7 having T3 of delay time. An AND circuit output g1 is supplied to the FF15, and supplied to an AND circuit 14 together with the output of the FF15, and an output (j) of the AND circuit 14 is ORed exclusively with the signal (b). |
