| 摘要 |
PURPOSE:To improve the information transfer efficiency of a common bus, by using the common bus for an address and control signal and a data signal in time division. CONSTITUTION:A CPU 2, information modules 3-5 and an arbitrating circuit 6 discriminating the priority are connected to the common bus 1. In this system, the address and control signal and the data signal are executed for time division transmission in synchronizing with a bus clock BCLK frequency-dividing a basic clock CLK so as to process information simultaneously at the modules 3-5. A module desiring to use the common bus inputs a bus request signal BREQ to the circuit 6 via the bus 1. The circuit 6 samples the signal BREQ and outputs a usage permission signal GRNT after the discrimination of the priority and admits the use of common bus. Even if the preceding module uses the common bus, when no address bus is used, the next module uses the address bus and even if a device having slow access time is connected, the deterioration of the data transmission efficiency is prevented. |
