发明名称 ERROR DETECTION SYSTEM
摘要 PURPOSE:To prevent an error occurring to some word from exerting influence upon the error detection of a next word, by increasing or decreasing the word digital sum value (WDS) of the next word when the error occurring to the precedent word is detected. CONSTITUTION:Transmitted data is inputted to an nB/mB code converter 1 and a WDS detector 2 to be outputted as (m)-bit data to an output terminal B, and the WDS of the (n)-bit data is found and sent to an adder 3. If RDS(output of flip-flop 4) is caused by a noise to deviates from a value (g) within a specific range + or -N to +N+alpha(h), comparing circuits 5 and 6 output ''1'' and ''0'' respectively and a selector 7 selects +N (information E) and outputs it to the Y terminal of the adder 3. The adder 3 adds the WDS of a next word inputted to the X terminal to said +N.
申请公布号 JPS595765(A) 申请公布日期 1984.01.12
申请号 JP19820115117 申请日期 1982.07.01
申请人 FUJITSU KK 发明人 HANABATAKE TOSHIO;WADA NOBUYUKI
分类号 H03M5/14;H04L25/49 主分类号 H03M5/14
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