发明名称 LIMITER WITH DYNAMIC HYSTERESIS
摘要 <p>Limiter circuit (13) with dynamic hysteresis for providing improved distortion immunity at the circuit output is response to an input signal. The limiter circuit (13) includes a positive (15) and negative peak detector (17). Two weighted averages are taken of the positive and negative peaks, preferably by means of a voltage divider network (18). The first input to a comparator circuit receives the input signal to the limiter circuit (13). Different voltages from the voltage divider network (18) are applied to the second input of the comparator circuit (21) so as to create a dynamic hysteresis effect in the comparator circuit (21). The different voltages are chosen in response to the output voltage from the comparator circuit (21) by means of an analog switch (19). The comparator circuit (21) includes a fixed hysteresis voltage for stabilizing the limiter circuit (13) at low level voltage input signals. </p>
申请公布号 WO1984000452(A1) 申请公布日期 1984.02.02
申请号 US1983001032 申请日期 1983.07.06
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