| 摘要 |
<p>A frequency synthesiser provided with frequency reduction means which includes a pulse swallow circuit PS which cancels cycles from the frequency Fo under the control of a rate multiplier RM. To prevent phase jitter at the output of phase comparator PC due to the cancelled cycles, a compensation signal HP is derived from the swallow command signal A and from the multiplying fraction n/x of the rate multiplier. In order to keep the DC level of the signal HP constant, the signal HP is bidirectional with respect to a mid-point voltage level and the total area of the pulses in one direction is the same as the total area of the pulses in the other direction. The invention is applicable to both phase locked loop synthesisers (Figure 2) and direct synthesisers (Figure 11).</p> |
