发明名称 |
System for distributed priority arbitration among several processing units competing for access to a common data channel |
摘要 |
A system for the exchange of messages among a multiplicity of processing units includes a data channel and a service line interconnecting respective interfaces of these units. Each interface includes a busy-state detector determining during a test phase of a recurrent time slot whether the service line is available, a logic network connectable in a subsequent acquisition phase the service line in the event of its availability to emit successive bits of an address characterizing the respective processing unit, and a comparator determining during the aquisition phase whether an emitted address bit of a particular logic level ("1") coincides with another bit of a higher-priority level ("0") concurrently sent over the line by some other unit. If a higher-priority address bit is encountered, the emission of the address is aborted and restarted in a subsequent time slot. If there is no conflict, an outgoing message is delivered to the data channel by way of a concurrently enabled driver; should that message require more than one time slot for its transmission, the service line is seized by the emission of a busy bit in the test phases of one or more subsequent time slots preceding the last time slot occupied by that message.
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申请公布号 |
US4470110(A) |
申请公布日期 |
1984.09.04 |
申请号 |
US19810318254 |
申请日期 |
1981.11.04 |
申请人 |
CSELT CENTRO STUDI E LABORATORI TELECOMMUNICAZIONI S.P.A. |
发明人 |
CHIAROTTINO, VOLMER;POGGIO, CESARE;REALI, ALDO |
分类号 |
G06F13/14;G06F13/374;(IPC1-7):G06F15/16;G06F9/46 |
主分类号 |
G06F13/14 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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