| 摘要 |
PURPOSE:To mask fault information with a mask part and to prevent the expansion of an effect of a faulty operation switch by holding the fault information on an operation switch which is defective in an initialization mode at a mask information register and controlling the mask part. CONSTITUTION:A CPU4, a mask register 7a and a fault information register 7b are set when a power supply is applied. If each push button of an operation switch 1 has a fault, the contents of this fault are set to an interruption input register 3. Then this register 3 is read to check the defective push button. The fault information is written in the register 7b, and the bit is set at an L level. In a normal flow mode, the output of an NOR gate 2i corresponding to a push- button switch 1i having a defective short circuit is set at an L level to obtain a state where the switch 1i is not pushed. This reduces the effect of a defective push-button switch.
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