| 摘要 |
PURPOSE:To generate a memory cycle start signal for accessing to a memory from a new bus master with a short loss time by providing a means which raises forcibly the memory cycle start signal. CONSTITUTION:The means which raises the memory cycle start signal forcibly by a DMA cycle signal at a DMA cycle start time is provided. For example, when a DMA controller 2 is started to become the bus master and the DMA cycle signal is raised to the high level, a 3-state buffer 5 is turned off, and a 3-state buffer 11 is turned on. An input signal ZO1 of the 3-state buffer 11 is applied to an MEM signal line 9, and an MEM signal is raised to the high level simultaneously with the start of the DMA cycle, and the memory access cycle is started with a very short loss time. During the processor cycle, said buffer 6 is turned on, and said buffer 11 is turned off, and the output from a processor 1 is applied to the MEM signal line 8.
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