| 摘要 |
<p>In a logic gate (14) having input transistors (QA, QB) each with a collector electrode at a first node (1) (which serves as a signal output node), an emitter electrode at a second node (2) to which all emitters are coupled and a base electrode for receiving binary logic signal input, and further having a load resistor (RL) between the first node (1) and a supply voltage coupling (VCC), the improvement in that means (16) are provided for controlling the emitter current at the second node (2) in response to voltage on the first node (1) in order to inhibit saturation of the input transistors (QA, QB) and to enhance switching speed of the logic gate (14). The emitter current controlling means (16) may include a current regulating transistor (Q5) coupled between the second node (2) and a ground reference wherein the base electrode thereof is coupled through a third node (3) to a biasing means (RF) coupled to the first node. The current regulating transistor (Q5) may be a Schottky transistor, that is, a transistor with a Schottky diode (D1) coupled between the base electrode and the collector electrode. The biasing means may be a feedback resistor (RF) coupled between the first node (1) and the third node (3). Voltage across the feedback resistor (RF) may be clamped to limit voltage range.</p> |
