Complementary logic integrated circuit.

摘要

A complementary logic circuit which has large power handling capacity, high switching speed and still has low power consumption is formed by a first stage comprising a complementary MIS-FET circuit (Q1, Q2), and an output stage comprising complementary bipolar transistors (Q3, Q4) or complementary vertical FETs. The output stage (Q3, Q4) is provided with pull-up and pull-down elements (lu, ID), for example in the form of resistors, for which pulling up or pulling down the amplitude of the output signal is set to a value almost equal to that of the power supply voltage. Accordingly, the defect consisting in the lack of amplitude in conventional Bi-MIS circuit to drive C-MIS circuits is eliminated and stable operation of C-MIS logic circuits is secured.