发明名称 DIGITAL TIME CONSTANT CIRCUIT
摘要 PURPOSE:To obtain a desired time constant even when the coefficient word length of a multiplier is not long enough by connecting an input signal line to the 1st input terminal of the 1st adder, and obtaining a signal with a specific time constant for an input signal at the output signal line on the 1st adder. CONSTITUTION:An input step signal line 101 is connected to an input terminal (a) of an adder 11 and an input terminal (b) of a subtracter 15, and the output signal line 111 of the adder 11 is connected to the input terminal (c) of a delay circuit 16, whose output signal line 161 is connected to an input terminal (d) of the subtracter 15. The output signal line 151 of this subtracter 15 is connected to the input terminal (e) of a 1/c scaling circuit 14 and an input terminal (f) of an adder 12, and the output line 141 of the circuit 14 is connected to the input terminal (g) of a multiplier 13, whose output signal line 131 is connected to an input terminal (h) of the adder 12; and the output line 121 is connected to an input terminal (i) of the adder 11 to obtain the signal with the specific time constant for the input step signal at the output line 111 of the adder 11.
申请公布号 JPS6081914(A) 申请公布日期 1985.05.10
申请号 JP19830190513 申请日期 1983.10.12
申请人 NIPPON DENKI KK 发明人 ENDOU YUKIO
分类号 H03H17/04;(IPC1-7):H03H17/04 主分类号 H03H17/04
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