发明名称 HIGH-SPEED COMMUNICATION SYSTEM
摘要 PURPOSE:To reduce the load of a computer and to reduce the execution time of a control program by providing a circuit between a circuit protocol LSI and a computer to share a part of the process that is executed by the computer when an interruption is produced from said LSI. CONSTITUTION:A terminal device 6, a computer 2 and a circuit control protocol LSI1 are connected via a data bus 9 and then connected to a memory 4, a DMA cintroller 3 and an interruption control circuit 10. The circuit 10 is connected to the LSI1 and the computer 2 via an interruption signal line 7. The memory 4 contains a control program store area (a), a transmission/reception data buffer area (b) and a control parameter area (c). The area (c) stores the DMA information, factors of transmission/reception interruptions, etc. When an interruption is produced, the circuit 10 shares a part of the process to be executed by the computer 2 by the interruption given from the LSI1. This reduces the load of the computer 2 and decreases the execution time of the control program.
申请公布号 JPS60158750(A) 申请公布日期 1985.08.20
申请号 JP19840013174 申请日期 1984.01.27
申请人 NIPPON DENKI KK 发明人 KUROIWA KENICHI
分类号 H04L29/02;G06F13/28;H04L13/00;H04L29/10 主分类号 H04L29/02
代理机构 代理人
主权项
地址