| 摘要 |
PURPOSE:To measure a small pulse width with a clock signal by holding outputs of a delay line group for delaying the clock signal at the time of starting and ending an unknown pulse signal. CONSTITUTION:Delay lines 7a-7d output a clock signal 4 delayed by one-fifth the cycle of each thereof 4. The signal 4 and delayed clock signals 17a-17d outputted from the delay lines 7a-7d are applied to data inputs of latches 8a-8j. A pulse signal 5 with an unknown pulse width is inputted into a driver 9, which outputs a latch pulse 14a at the rising time of the signal 5 while a latch pulse 14b at the falling time thereof. Outputs of the latches 8a-8j are applied to an address terminal of a ROM10, a phase signal 11 as output of the ROM10 is added to the lower word of a signal of a counter 3 to obtain a pulse width signal 13 having a resolving power equivalent to one-tenth the cycle of the signal 4.
|
